Toshiba develops circuit techniques for embedded SRAM operating at 0.5V-1.0V

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Toshiba Corp has developed circuit techniques for embedded SRAM that operate in a wide supply voltage range, from 0.5V to 1.0V, that effectively contribute to lower power consumption by electronic devices.

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The test chip fabricated employs three new techniques to ensure proper operation of SRAM even when the operating voltage varies. At the same time, cell failure rate is reduced and fast operation is achieved. Toshiba has demonstrated these techniques in a 40nm 2Mb SRAM test chip at 0.5V operation.

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The chip employs three new techniques to achieve stable operation even when the voltage varies or is low.

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Embedded SRAM in LSI for mobile equipment have multiple cells for data storage and must achieve stable performance even if cell characteristics vary. Conventional SRAM techniques employ wordline selection signals for read/write operations. As operating conditions, such as transistor thresholds, temperature and voltage, vary, the optimum wordline voltage at which SRAM cells properly operate also changes.

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Toshiba’s new circuit technique predicts SRAM cell failure rate in real time and automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary. The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit technique also eliminates the need to program the wordline level voltage chip by chip, which conventional SRAM require.

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